1. Field of the Invention
The present invention relates to an insulated gate N-channel field effect transistor having a withstand voltage of 10 V or more at a semiconductor substrate which can incorporate a Bipolar or CMOS and on which an epitaxial layer is formed. The present invention also relates to a semiconductor device including this insulated gate N-channel field effect transistor.
2. Description of the Related Art
FIG. 5 is a sectional view of an example of BiCMOS integrated circuits, which is manufactured by using a P-type semiconductor substrate 1 and through an N-type epitaxial step. An N-channel insulated gate field effect transistor 101 is formed in a P-type well layer 4 formed in an N-type epitaxial layer 2. A P-type insulated gate field effect transistor 102 is formed in a region of the N-type epitaxial layer 2. An NPN vertical bipolar transistor 103 is manufactured in such a manner that a P-type base diffusion region 15 and an N-type sinker 14 are formed in the N-type epitaxial layer 2 on an N-type buried layer 13. Separation between respective elements, especially, the separation between the insulated gate field effect transistor and the bipolar transistor can be made in such a manner that a P-type buried layer 3 and the P-type well layer 4 are subjected to diffusion from an upper side and a lower side of the N-type epitaxial layer and are brought into contact with each other.
The thickness of the N-type epitaxial layer depends on the performance of an objective integrated circuit. As an example, when the withstand voltage of the NPN vertical bipolar transistor is set to 15 V or more, preferably the thickness thereof is set to 4 xcexcm or more. As for the N-type sinker 14, for the purpose of lowering collector resistance and lowering h fe of a parasitic bipolar, the concentration thereof is preferably selected from a range of 5xc3x971017 to 1xc3x971019/cm3. Also, the depth thereof is preferably selected from a range of 3 to 5 xcexcm.
FIG. 2 is a sectional view of an example of an insulated gate N-channel field effect transistor used at a semiconductor substrate including an epitaxial layer in a BiCMOS integrated circuit.
Reference numeral 1 denotes a semiconductor substrate, and a P-type semiconductor substrate is generally used. An N-type epitaxial layer 2 of 1xc3x971014 to 1xc3x971016/cm3 is formed on this P-type semiconductor substrate, and elements are formed therein. In case of the N-channel insulated gate field effect transistor, a P-type well layer 4 and optionally a P-type buried layer 3 are formed, and BiCMOS integrated circuit is formed in this P-type region. Reference numerals 5 and 6 each denote a source region and a drain region of the insulated gate field effect transistor, in which P (Phosphorus) or As (Arsenite) is implanted to make the concentration as high as 1xc3x971020/cm3 or more. A gate electrode 8 is formed over a channel forming region 11 through a gate insulating film 7. However, an N-type low concentration region 9 of 1xc3x971016 to 1xc3x971018/cm3 is formed between the drain region 6 and the channel forming region 11, with the result that a withstand voltage between the drain and source can be raised as compared with the case where this low concentration region does not exist.
This is because a depletion layer on the drain side is apt to extend in this low concentration region as compared with general insulated gate field effect transistors. As a result, there is an effect to suppress the avalanche breakdown from occurring in the junction between the drain region and the channel forming region. The length of this low concentration region depends on a desired withstand voltage. However, the length is preferably set between 1.5 xcexcm and 3 xcexcm in the case where the desired withstand voltage is within a range of 15 V to 40 V. When the insulating film on the N-type low concentration region is made thicker than the gate insulating film, it is possible to avoid occurrence of a high electric field between the gate and drain, as well as preventing a leak and breakdown caused by this. It is preferable to set the thickness of this insulating film 10 thicker than the gate insulating film be 0.1 xcexcm or more. For example, a field insulating film for separating elements may also be used as the film.
However, the insulated gate field effect transistor having the structure of FIG. 2 has a low ESD (electric static discharge) strength. Accordingly, there is a defect in that when a drain terminal is connected to an external pad, junction breakdown is liable to occur in the N-type low concentration region by static electricity entering the drain terminal from outside. In order to prevent the breakdown by the static electricity, for example, there is a method in which a specific protective element is provided at a wiring line communicating with a pad in a circuit. However, by providing this protective element, an area of a semiconductor integrated circuit is increased, resulting in an increase of the cost. In order to improve the ESD strength of the insulated gate type transistor without using the protective element (for preventing an increase of an area of a semiconductor integrated circuit), as shown in FIG. 3, there is a method in which a deep N-type diffusion region 12 is formed around a high concentration drain region as a center, for instance. However, this method also causes a cost increase arising from the increase of steps, since a mask step and a diffusion step must be newly added to form the N-type diffusion region. The higher the concentration of the N-type diffusion layer 12 is, and the deeper the depth of diffusion from the surface of the N-type epitaxial layer 2 is, the better the ESD strength can be increased. For example, in the case of HBM (human body model), in order to obtain an ESD strength of 2 kV or more, it is appropriate that the concentration of the N-type diffusion layer is 1xc3x971016/cm3 or more and the depth is 1.5 xcexcm or more.
As described above, in the insulated gate field effect transistor, for the purpose of making the high withstand voltage compatible with the high ESD strength, it is impossible to avoid the increase in the step corresponding to one masking process. In addition, a potential (herein referred to as xe2x80x9cbody potentialxe2x80x9d to be distinguished from a potential of the P-type semiconductor substrate) of a region of this element where a channel is formed becomes the same as a potential of the P-type semiconductor substrate that is the lowest potential on the circuit. Therefore, an application to a multi-system power source IC including a charge pump circuit having a circuit structure in which the element has a body potential different from the lowest potential on the circuit is difficult.
Then, for the purpose of solving such a problem inherent in the prior art, an object of the present invention is to make the high withstand voltage and high ESD strength of an insulated gate field effect transistor compatible with each other without using a protective element and without increasing steps, thereby realizing an element structure in which a body potential of the element can be freely changed.
In order to solve the above problem, according to the present invention, there is provided an insulated gate N-channel field effect transistor, comprising:
a source region and a drain region, each having an N-type and high concentration, formed on an N-type epitaxial layer formed on a P-type semiconductor substrate with an interval;
a channel forming region between the source region and the drain region;
a gate electrode formed through the channel forming region and a gate insulating film;
an N-type low concentration region formed between the drain region and the channel forming region;
an insulating film formed on the low concentration region and thicker than the gate insulating film;
a P-type well layer in a region including the source region, the channel forming region, and a part of the region under the insulating film thicker than the gate insulating film, and surrounding the drain region
an N-type buried layer formed in a region, which is a boundary between the semiconductor substrate and the epitaxial layer, including the source region, the drain region, the channel forming region, and a region under the insulating film thicker than the gate insulating film; and
a P-type buried layer including the source region, the drain region, the channel forming region, and a region under the insulating film thicker than the gate insulating film, the P-type buried layer being contained within the N-type buried layer as viewed from above and being formed beyond the upper and lower sides of the N-type buried layer in its depth direction, the upper portion of the P-type buried layer having a width extending to the P-type well layer from the upper side of the N-type buried layer.
The insulated gate N-channel field effect transistor set forth in the above, further comprises:
an N-type low concentration region formed between the drain region and the channel forming region;
an insulating film formed on the low concentration region and is thicker than the gate insulating film;
an N-type low concentration region formed between the source region and the channel forming region;
an insulating film formed on the low concentration region and is thicker than the gate insulating film; and
a P-type well layer in a region including the channel forming region, and a part of the region under the insulating film thicker than the gate insulating film, and surrounding the drain region and the source region.